1. Field
The present invention relates to systems and techniques for verifying mask patterns.
2. Related Art
Lithography processing represents an essential technology for manufacturing Integrated Circuits and Micro-Electro-Mechanical Systems (MEMS) and Nano-Electro-Mechanical Systems (NEMS). Lithographic techniques are used to define: patterns, geometries, features, shapes, etc. onto an integrated-circuit die, semiconductor wafer, or chips. These patterns are typically defined by: a set of contours, lines, boundaries, edges, curves, etc., which generally surround, enclose, and/or define the boundary of the various regions which constitute the patterns.
One existing lithographic technique is photolithography, in which images defined by photo-masks are printed onto an integrated-circuit die or one or more semiconductor wafers. Unfortunately, it is increasingly difficult to design and manufacture photo-masks.
In particular, demand for increased density of features on the integrated-circuit die and the one or more semiconductor wafers has resulted in the design of circuits with decreasing minimum dimensions. These trends have significantly increased the complexity of the computations necessary to determine the mask patterns (to which the photo-masks correspond), with a commensurate impact on computation time, processing requirements, and expense.
Furthermore, due to the wave nature of light, as dimensions approach sizes comparable to the wavelength of the light used in the photolithography processes, the resulting wafer patterns deviate from the corresponding photo-mask patterns and are accompanied by unwanted distortions and artifacts. Existing techniques (such as Optical Proximity Correction or OPC, and Resolution Enhancement Technologies or RED are used to pre-distort the mask patterns to improve resolution and/or a process window (e.g., a range of process conditions that result in acceptable yield) in a photolithography process. While these techniques may ensure that the wafer pattern is printed more accurately, determining the pre-distorted mask patterns is increasingly difficult, thereby exacerbating the computational complexity and the associated problems.
Additionally, it is also increasingly difficult to verify that the resulting mask patterns meet predefined design criteria. In particular, as the minimum dimensions of features in the mask patterns are reduced and the complexity of the mask patterns is increased, differences or defects can occur between the wafer patterns produced using the mask pattern and desired target patterns. While some of these defects are more important than others, it is increasingly difficult to assess the relative importance of the defects.
Hence, what is needed is a method and an apparatus that facilitates verification of mask patterns without the above-described problems.